Integrated circuits (ICs) may be designed and built with additional hardware and software configured to perform self-test. A built-in-self-test (BIST) system enables an integrated circuit to test its own functions and operations. In some cases, an integrated circuit does not need external automated self-test equipment to verify its functionality. Typically, BIST systems generate test signal patterns to run through the internal circuits of an IC and then collect the responses from various internal components to determine whether the response matches a predetermined expected response. High data rate ICs may especially benefit from careful characterization, production testing, and in-system debug capability. If specialized and expensive (e.g. typical cost >$100 k) bit error ratio testers and oscilloscopes are required, then such requirement limits the ability to use off the shelf, low-cost automated test equipment (ATE).
In many digital data communication applications, communication is bi-directional, and ICs that include a combination of a transmitter and receiver are used at both ends of a communication link. This combination is also known as a transceiver. In transceivers, a “loopback” test function provides a functional “at device speed” test. A BIST can generate test patterns for the transmitter that can be looped back to the receiver. This enables testing of the receiver function at device speed within the transceiver IC. In other digital communication applications using integrated circuits, communications are in a single direction where an upstream transmitter communicates to a downstream receiver. One common example is a video interface for a display device, which is a “receive only” device without transmission capability. Other devices include processors, video controllers, field programmable gate arrays (FPGA), or application specific integrated circuits (ASIC), which send data to display devices.
In transceiver systems, the loopback BIST function only provides a pass/fail indication and does not provide device margin measurements. In loopback functions, direct measurement of signals that a receiver actually receives is not practical, because the “loop” is completed within the device. The closest measurements that can be made are typically at external pads/pins of the device. These pads/pins can be probed, but additional signal degradation (such as reflections caused by plating stubs, bond wires and/or non-ideal termination) is not measured. For standalone receivers, challenges exist in testing receiver functions at the device speed, because the testing is conducted using external connections, which may introduce noise and other interference that skews the test results. In a high speed communications system, signal integrity of electrical signals is important for an error free, robust link.
FIG. 1 shows an example “data eye” diagram, which is useful to evaluate the performance of a communication link. In data eye diagram measurement, timing and voltage margins can be directly measured. This is typically done using a high speed oscilloscope connected to external boundaries or test connections (e.g., pins, balls or pads) of a packaged IC. As the eye becomes more “open” in the vertical direction, more voltage margin (measured as the amplitude of the eye) becomes available to the receiver. Similarly, as the “eye” becomes more open in the horizontal direction, more timing margin (measured as the width of the eye) becomes available to the receiver.
This measurement has several drawbacks. First, it uses an expensive oscilloscope, which may be unavailable in a test environment, and likewise may be unavailable in a completed or assembled system. Second, by measuring at the external boundary of the packaged IC, the data eye diagram does not provide a complete view of the device's internal functioning.
FIG. 2 shows an example circuit 200 with conventional methods of testing and measurements. Circuit 200 includes a receiver circuit 205 configured to receive data only (e.g., display unit). Circuit 200 further includes a transmitter 210. Transmitter 210 can be any circuit configured to transmit data downstream to the receiver 205. The data from transmitter 210 travels through transmission line 220 (e.g., circuit paths on a circuit board). The data is received by the receiver 205 at an entrance point 230 of the receiver 205 circuit package. The entrance point 230 can be any circuit connection, such as a pin grid array (PGA), land grid array (LGA), and similar other IC package connections. The IC package introduces parasitic inductance and capacitance 235 in the signal path. The signal further travels through the internal routings 240 of the receiver 205 and can introduce further signal abnormalities due to various factors, such as bond-wire inductance 250. The signal is eventually received in the IC at termination point 260. The termination point 260 can further introduce parasitic capacitance to the incoming signal resulting from electrostatic discharge (ESD) protection circuits, IC bond-pads, and the IC active circuitry in the receiver.
In conventional testing methods, signals are tested at the transmitter's exit points and the receiver's entry points, without measuring the voltage and timing margins inside the receiver 205 at the termination point 260. For example, when the signal is initially tested at the output of the transmitter 210, it may illustrate an ideal data eye diagram 270. However, when the measurements are conducted at the entry point 230 and termination point 260, the data eye diagram may be represented as shown in eye diagrams 280 and 290 respectively. This is due to further signal loss, reflections, filtering and equalization, resulting from non-idealities and electrical behavior of the IC package and/or the IC die. The data eye diagrams provide different margins for voltage and time at each signal point. As shown, conventional testing methods fail to provide data on the receiver's voltage and timing margins.